Testing of semiconductor chips has been challenging for many manufacturers due to its impact on production costs. Many measures including increase of test system throughputs have been implemented to cut testing costs. For example, parallel testing of multiple dies was introduced in automated test systems, such as automated test equipment (ATE), in order to cut testing costs. However, at the wafer level in which a wafer has hundreds of chips, parallel testing becomes difficult due to the need for multiple input/output (IO) channels for each semiconductor chips. Therefore, a need exists for a method and system to perform parallel wafer level testing on multiple semiconductor chips that requires less resource from the automated test systems.